1. Field of the Invention
The present invention is related to a delay lock loop system, and particularly to a delay lock loop system with a self-tracking function.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a delay lock loop 100 according to the prior art. When the delay lock loop 100 enters a power saving mode, circuit units included by the delay lock loop 100 are disabled. Please refer to FIG. 2A and FIG. 2B. FIG. 2A is a diagram illustrating a capacitor 102 leaking in the power saving mode (meanwhile, a power saving signal CKE is at a logic-low voltage), resulting in a voltage of a control node VCTRL controlling a voltage control delay circuit 104 being reduced. FIG. 2B is a diagram illustrating the delay lock loop 100 having a greater phase error because of a reduced voltage of the control node VCTRL when the delay lock loop 100 is enabled again. As shown in FIG. 2A, when the delay lock loop 100 enters the power saving mode, energy stored in the capacitor 102 decreases gradually until the delay lock loop 100 is enabled again. Therefore, as shown in FIG. 2B, when delay lock loop 100 is enabled again, the delay lock loop 100 has the greater phase error, because the delay lock loop 100 has to recharge a leakage of the capacitor 102 (that is, the reduced voltage of a control node VCTRL). In addition, please refer to FIG. 2C. FIG. 2C is a diagram illustrating a relationship between a temperature of the delay lock loop 100 and delay time of the delay lock loop 100. As shown in FIG. 2C, when the delay lock loop 100 is enabled again, delay time of the delay lock loop 100 is shorter than delay time of the delay lock loop 100 operating at a normal temperature T, because the temperature of the delay lock loop 100 is decreased gradually during the power saving mode. Therefore, when the power saving signal CKE is changed from the logic-low voltage to a logic-high voltage (that is, the delay lock loop 100 is enabled again), the delay lock loop 100 has the greater phase error, because the delay lock loop 100 has the shorter delay time.